Run-Time Reconfigurable FFT Engine

Authors

  • Ahmad F. Al-Allaf Technical college-MOSUL Dept of Computer eng.
  • Shefa A. Dawwd College of Engineering Dept of Computer Eng. MOSUL University

Keywords:

Fast Fourier Transform, Radix-4, FPGA, Run time Reconfiguration

Abstract

This paper develops a system level architecture for implementing a cost-efficient, FPGA-based realtime FFT engine. This approach considers both the hardware cost (in terms of FPGA resource requirements), and performance (in terms of throughput). These two dimensions are optimized based on using run time reconfiguration, double buffering technique and the hardware virtualization to reuse the available processing components. The system employs sixteen reconfigurable parallel FFT cores. Each core represents a 16 complex point parallel FFT processor, running in continuous realtime FFT engine. The architecture support transform length of 256 complex points, as a demonstrator to the idea design, using fixed-point arithmetic and has been developed using radix-4 architecture. The parallel Booth technique for realizing the complex multiplier (required in the basic butterfly operation) is chosen. That is to save a lot of hardware compared to other techniques. The simulation results that have been performed using VHDL modeling language and ModelSim software

shows that the full design can be implemented using single FPGA platform requiring about 50,000 Slices.

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Published

24-03-2010

How to Cite

Al-Allaf, A. F., & Dawwd, S. A. (2010). Run-Time Reconfigurable FFT Engine. Al-Nahrain Journal for Engineering Sciences, 13(2), 150–157. Retrieved from https://nahje.com/index.php/main/article/view/592

Issue

Vol. 13 No. 2 (2010): Al-Nahrain University, College of Engineering Journal (NUCEJ)

Section

Articles

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